Sitemap - 2024 - Chips and Cheese
Skymont in Desktop Form: Atom Unleashed
Rebellions: From High Frequency Trading to AI Acceleration
Fujitsu's Monaka CPU: ARMv9, SVE2, and 3D Stacking
Turning off Zen 4's Op Cache for Curiosity and Giggles
400G Omnipath is Coming: Cornelis Networks at SC24
Examining Intel's Arrow Lake, at the System Level
An EPYC Exclusive for Azure: AMD's MI300C
AMD Disables Zen 4's Loop Buffer
NextSilicon: Putting HPC First
Ayar Labs at Supercomputing 2024: Making Light Move Bits (YouTube Short)
Pushing AMD’s Infinity Fabric to its Limits
Supercomputing 2024: El Capitan, MI300A, and More on the Fastest Supercomputers!
Chips and Cheese's Microbenchmark Framework
AMD's 9800X3D: 2nd Generation V-Cache
Broadwell’s eDRAM: VCache before VCache was Cool
Stability, The Cost Of Intel's Time To Market Approach (Video)
Running SPEC CPU2017 on Chinese CPUs, and More
AMD's Turin: 5th Gen EPYC Launched
Lunar Lake’s iGPU: Debut of Intel’s Xe2 Architecture
The Next Stage for Chips and Cheese
Skymont: Intel’s E-Cores reach for the Sky
Chips and Cheese Interviews Ronak Singhal
Lion Cove: Intel’s P-Core Roars
Intel Granite Rapids: A Step in the Right Direction (Video)
Intel’s Redwood Cove: Baby Steps are Still Steps
Running SPEC CPU2017 at Chips and Cheese?
Discussing AMD’s Zen 5 at Hot Chips 2024
FuriosaAI’s RNGD at Hot Chips 2024: Accelerating AI with a More Flexible Primitive
Telum II at Hot Chips 2024: Mainframe with a Unique Caching Strategy
An Interview with Susan Eickhoff and Christian Jacobi from IBM at Hot Chips 2024
An Interview with Intel’s Arik Gihon about Lunar Lake at Hot Chips 2024
AmpereOne at Hot Chips 2024: Maximizing Density
Tesla’s TTPoE at Hot Chips 2024: Replacing TCP for Low Latency Applications
Hot Chips 2024: Qualcomm’s Oryon Core
AMD’s Radeon 890M: Strix Point’s Bigger iGPU
Zen 5 Variants and More, Clock for Clock
AMD’s Ryzen 9950X: Zen 5 on Desktop
AMD’s Strix Point: Zen 5 Hits Mobile
Cortex A73’s Not-So-Infinite Reordering Capacity
Grace Hopper, Nvidia’s Halfway APU
Zen 5’s 2-Ahead Branch Predictor Unit: How a 30 Year Old Idea Allows for New Tricks
Arm’s Neoverse V2, in AWS’s Graviton 4
Arm’s Cortex A73: Resource Limits, What are Those?
A Video Interview with Mike Clark, Chief Architect of Zen at AMD
Qualcomm’s Oryon Core: A Long Time in the Making
The Snapdragon X Elite’s Adreno iGPU
Examining the Nintendo Switch (Tegra X1) Video Engine
Testing AMD’s Bergamo: Zen 4c Spam
Tracing Intel’s Atom Journey: Goldmont Plus
Intel’s Lion Cove Architecture Preview
Update on Meteor Lake DRAM Latency Measurements
Comparing Crestmonts: No L3 Hurts
Meteor Lake’s E-Cores: Crestmont Makes Incremental Progress
Chips and Cheese State of the Union
Inside the Snapdragon 855’s iGPU
Can China’s Loongson Catch Western Designs? Probably Not.
Sizing up Qualcomm’s 8cx Gen 3 iGPU
Raytracing on Meteor Lake’s iGPU
Intel’s Ambitious Meteor Lake iGPU
Inside Control Data Corporation’s CDC 6600
The Nerfed FPU in PS5’s Zen 2 Cores
Loongson 3A6000: A Star among Chinese CPUs
Inside Snapdragon 8+ Gen 1’s iGPU: Adreno Gets Big
AMD’s Mild Hybrid Strategy: Ryzen Z1 in ASUS’s ROG Ally
Examining AMD’s RDNA 4 Changes in LLVM
Inside Qualcomm’s Adreno 530, a Small Mobile iGPU