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January 2025

A RISC-V Progress Check: Benchmarking P550 and C910
RISC-V has seen a flurry of activity over the past few years.
 • 
Chester Lam
23
Inside SiFive’s P550 Microarchitecture
RISC-V is a relatively young and open source instruction set.
 • 
Chester Lam
15
Disabling Zen 5’s Op Cache and Exploring its Clustered Decoder
Zen 5 has an interesting frontend setup with a pair of fetch and decode clusters.
 • 
Chester Lam
4
Sizing up MI300A’s GPU
AMD’s Instinct MI300A is a giant APU, created by swapping out two GPU chiplets (XCDs) for three CPU chiplets (CCDs).
 • 
Chester Lam
2
Inside the AMD Instinct MI300A's Giant Memory Subsystem
AMD acquired ATI in 2006, hoping ATI's GPU expertise would combine with AMD's CPU know-how to create integrated solutions worth more than the sum of…
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Chester Lam
13
Nvidia's Announcements at CES 2025
Hello you fine Internet folks,
 • 
George Cozma
1
AMD's Strix Halo - Under the Hood
Hello you fine Internet folks,
 • 
George Cozma
13
AMD's CES 2025 Keynote
Hello you fine Internet folks,
 • 
George Cozma
3
Intel's CES 2025 Keynote
Hello you fine Internet folks,
 • 
George Cozma
2
Digging into Driver Overhead on Intel's B580
Hardware Canucks recently found that Intel's new B580 GPU suffered when paired with older, weaker CPUs.
 • 
Chester Lam
13
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