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AMD's Strix Halo - Under the Hood
Hello you fine Internet folks,
Jan 13
•
George Cozma
3
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AMD's Strix Halo - Under the Hood
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AMD's CES 2025 Keynote
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Jan 12
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George Cozma
4
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AMD's CES 2025 Keynote
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Intel's CES 2025 Keynote
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Jan 9
•
George Cozma
8
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Intel's CES 2025 Keynote
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2
Digging into Driver Overhead on Intel's B580
Hardware Canucks recently found that Intel's new B580 GPU suffered when paired with older, weaker CPUs.
Jan 8
•
Chester Lam
21
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Digging into Driver Overhead on Intel's B580
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12
Analyzing Lion Cove's Memory Subsystem in Arrow Lake
A CPU core can perform very differently depending on the platform it's deployed in.
Jan 6
•
Chester Lam
12
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Analyzing Lion Cove's Memory Subsystem in Arrow Lake
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9
NeuReality: A Server on a PCIe Card
Or a DPU for AI accelerators
Jan 4
•
George Cozma
5
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NeuReality: A Server on a PCIe Card
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d-Matrix Corsair: 256GB of LPDDR for AI Models
With Microscaling Number Formats to boot!
Jan 1
•
George Cozma
10
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d-Matrix Corsair: 256GB of LPDDR for AI Models
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1
December 2024
IBM Power - What's Next?
An Interview with Bill Starke
Dec 27, 2024
•
George Cozma
7
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IBM Power - What's Next?
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5
Skymont in Desktop Form: Atom Unleashed
Skymont is Intel's newest E-Core architecture.
Dec 20, 2024
•
Chester Lam
16
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Skymont in Desktop Form: Atom Unleashed
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Rebellions: From High Frequency Trading to AI Acceleration
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Dec 17, 2024
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George Cozma
6
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Rebellions: From High Frequency Trading to AI Acceleration
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Fujitsu's Monaka CPU: ARMv9, SVE2, and 3D Stacking
Designed for the datacenter and due in 2027
Dec 13, 2024
•
George Cozma
19
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Fujitsu's Monaka CPU: ARMv9, SVE2, and 3D Stacking
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1
Turning off Zen 4's Op Cache for Curiosity and Giggles
CPUs start executing instructions by fetching those instruction bytes from memory and decoding them into internal operations (micro-ops).
Dec 11, 2024
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Chester Lam
17
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Turning off Zen 4's Op Cache for Curiosity and Giggles
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