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Turning off Zen 4's Op Cache for Curiosity and Giggles
CPUs start executing instructions by fetching those instruction bytes from memory and decoding them into internal operations (micro-ops).
 • 
Chester Lam
4
400G Omnipath is Coming: Cornelis Networks at SC24
Hello you fine Internet folks,
 • 
George Cozma
Examining Intel's Arrow Lake, at the System Level
Arrow Lake is the codename for Intel's newest generation of high performance desktop CPUs.
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Chester Lam
7
An EPYC Exclusive for Azure: AMD's MI300C
The pun was just too good to resist.
 • 
George Cozma
3

November 2024

AMD Disables Zen 4's Loop Buffer
A loop buffer sits at a CPU's frontend, where it holds a small number of previously fetched instructions.
 • 
Chester Lam
2
NextSilicon: Putting HPC First
Not an FPGA, not a GPU, but something different!
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George Cozma
2
Ayar Labs at Supercomputing 2024: Making Light Move Bits (YouTube Short)
Hello you fine Internet folks,
 • 
George Cozma
Pushing AMD’s Infinity Fabric to its Limits
I recently wrote code to test memory latency under load, seeking to reproduce data in various presentations with bandwidth on the X axis and latency on…
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Chester Lam
13
Supercomputing 2024: El Capitan, MI300A, and More on the Fastest Supercomputers!
There's a new Number One for the 64th TOP500 list
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George Cozma
1
Chips and Cheese's Microbenchmark Framework
A Call to Action for Code Contributors
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George Cozma
5
AMD's 9800X3D: 2nd Generation V-Cache
Following the first generation of V-Cache found in the Zen 3 and Zen 4 X3D SKUs, AMD is now following up with the second generation of V-Cache which is…
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George Cozma
6
Broadwell’s eDRAM: VCache before VCache was Cool
Up to Haswell’s 2013 release, Intel’s “tick-tock” strategy seemed unstoppable.
 • 
Chester Lam
13
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