I recently wrote code to test memory latency under load, seeking to reproduce data in various presentations with bandwidth on the X axis and latency on the Y axis.
Overclocking ddr5 is quite easy, both hynix 16gbit A-die and 24gbit M-die should clock past 8000MT/s on adequate hardware, even if they come from DDR5-6000 kits.
I would love to see Zen 3 and Zen or Zen+ here as well.
And it does seem that AMd indeed did some tweaking, even though I do bemoan them that they didn't change IO Die.
One thing though. Zen 5 IF fabric was clocked at 10% higher than Zen 4. And sometimes result is 10% better (Bandwidth Load, nearly all cores) - is this the result of that or not relevant here?
Are you based in UK or US? I think I have both Zen+ and Zen 3. Though IDK if the configuration would be perfect (both were replaced by "better" models) - 2700X is definitely available. If it is to UK, it shouldn't be a problem to send it from Poland.
Yeah. It makes it a bit hard. I can ask some of my friends there if they have a spare Zen+ or Zen 3 that they won't be using anymore and won't be giving out to someone else, but shipping to US gets complex and packing is... a chore.
Take care of your health primarily. As much as I'd love to see more tests and "evolution of Zen" it cannot ever come at the cost of someone's health.
Are the epyc parts with two or four CCDs able to benefit from extra memory bandwidth available in the Siena (6 channel) and Turin (12 channel) platforms. Specifically CPUs like the 16 core Epyc 8124P or the 16 core Epyc 9115?
Do any of those similar parts enable a 2nd IF port to the CCD to make the most of the memory bandwidth available to the socket?
Yes, at https://chipsandcheese.com/p/amds-turin-5th-gen-epyc-launched Cheese/George ran my memory bw and latency testing code on Turin. A single CCD is able to get over 100 GB/s on its own thanks to the duplicated IF links. I also ran an earlier version of my loaded memory BW test on that system
Is there a possibility to get your program for testing memory latency/L3 bandwidth?
it's on my Github account (https://github.com/clamchowder/Microbenchmarks), though don't expect good documentation or any level of support
Thank you kind sir
Overclocking ddr5 is quite easy, both hynix 16gbit A-die and 24gbit M-die should clock past 8000MT/s on adequate hardware, even if they come from DDR5-6000 kits.
I would love to see Zen 3 and Zen or Zen+ here as well.
And it does seem that AMd indeed did some tweaking, even though I do bemoan them that they didn't change IO Die.
One thing though. Zen 5 IF fabric was clocked at 10% higher than Zen 4. And sometimes result is 10% better (Bandwidth Load, nearly all cores) - is this the result of that or not relevant here?
Clocking IF 10% higher can give 10% better bandwidth from 1 CCD, yes.
I don't have a Zen 3 or Zen(+) system on hand. I tested what I had easy access to.
Are you based in UK or US? I think I have both Zen+ and Zen 3. Though IDK if the configuration would be perfect (both were replaced by "better" models) - 2700X is definitely available. If it is to UK, it shouldn't be a problem to send it from Poland.
I'm in the US. I assume that makes things difficult
I could rent Zen 1/3 Epyc instances from cloud providers at some point. I do want to look at server systems anyway, whenever I find free time
Yeah. It makes it a bit hard. I can ask some of my friends there if they have a spare Zen+ or Zen 3 that they won't be using anymore and won't be giving out to someone else, but shipping to US gets complex and packing is... a chore.
Take care of your health primarily. As much as I'd love to see more tests and "evolution of Zen" it cannot ever come at the cost of someone's health.
Are the epyc parts with two or four CCDs able to benefit from extra memory bandwidth available in the Siena (6 channel) and Turin (12 channel) platforms. Specifically CPUs like the 16 core Epyc 8124P or the 16 core Epyc 9115?
Do any of those similar parts enable a 2nd IF port to the CCD to make the most of the memory bandwidth available to the socket?
Yes, at https://chipsandcheese.com/p/amds-turin-5th-gen-epyc-launched Cheese/George ran my memory bw and latency testing code on Turin. A single CCD is able to get over 100 GB/s on its own thanks to the duplicated IF links. I also ran an earlier version of my loaded memory BW test on that system
Do you know if all the 64c and smaller Turin chips use the GMI3-W, or just the top of the line "F" chips like the 9575F?
I think Star Citizen would be a good game to have look at, some benchmarks is showing it to be much more memory speed sensitive
Amd has mentioned that their bottleneck is feeding the cores.
I explore whether the limits can go both ways: https://github.com/EI2030/Low-power-E-Paper-OS/blob/master/Hyperlinks%20and%20Scratchpad.md#can-infinity-fabric-be-applied-to-the-low-end