Yep, GPUs have supported virtual memory for a long time. AMD's GCN had it, and even later Terascale versions (like Terascale 2 in Llano) had virtual memory support.
Yep, GPUs have supported virtual memory for a long time. AMD's GCN had it, and even later Terascale versions (like Terascale 2 in Llano) had virtual memory support.
Hmm. I forgot graphics GPUs were integrated, of course. I was thinking more of the AI GPUs. I would expect Nvidia GPUs like H100 have no virtual paging on their HBM but they could use it through PCIe/ATS to work with the host memory.
With the MI300A everything is HBM, and I would have expected the XCDs to have a stripped-down direct map to the HBM. But maybe AMD made the XCD virtual?
Yep, GPUs have supported virtual memory for a long time. AMD's GCN had it, and even later Terascale versions (like Terascale 2 in Llano) had virtual memory support.
Hmm. I forgot graphics GPUs were integrated, of course. I was thinking more of the AI GPUs. I would expect Nvidia GPUs like H100 have no virtual paging on their HBM but they could use it through PCIe/ATS to work with the host memory.
With the MI300A everything is HBM, and I would have expected the XCDs to have a stripped-down direct map to the HBM. But maybe AMD made the XCD virtual?
Discrete GPUs have virtual memory support too, so GCN had page tables (though used virtually addressed caches so no TLB lookups on cache hit).
Applies to Nvidia as well, at least since Pascal (https://nvidia.github.io/open-gpu-doc/pascal/gp100-mmu-format.pdf) but NV likely had virtual memory support well before that
Very interesting, thank you. Yes there was paging before Pascal, I found documentation for the changes when Pascal was done.
https://nvidia.github.io/open-gpu-doc/pascal/
The HBM paging seems to be 2MB large pages and the MMU generally is flexible to address the host.
https://arxiv.org/html/2408.11556v2