> Strix Halo is the big APU ... with the full fat 512b FPU
I've been wondering about this -- where do we know this from? Did they mention it in the keynote? (Also do we know if the CPU half will have full access to all the memory bandwidth (vs. only the GPU)? I assume it would, but last time I speculated about the former question, I received counterspeculation about the latter...)
> Strix Halo is the big APU ... with the full fat 512b FPU
I've been wondering about this -- where do we know this from? Did they mention it in the keynote? (Also do we know if the CPU half will have full access to all the memory bandwidth (vs. only the GPU)? I assume it would, but last time I speculated about the former question, I received counterspeculation about the latter...)
Its a MCM design and integrates the regular Ryzen/Epyc/TR CCDs. They could even use CCDs with 3D cache if they wanted.
I was wondering the same. I was even thinking that even Fire Range may not use the full 512b FPU.
Why MultiChipModule ensures that it uses the regular Ryzen/Epyc CCD?