Hello you fine Internet folks,
AMD held a keynote at CES 2025 about their upcoming products in the form of dual CCD V-Cache for Zen 5 CPUs, Fire Range, Kraken, Strix Halo, along with the surprising lack of anything RDNA4 and FSR4 other than it's coming later this quarter.
Starting with the dual CCD V-Cache Zen 5 CPUs and the layout is the same as Zen 4 with V-Cache so there is only one CCD with V-Cache with the other CCD being a standard non V-Cache CCD that is able to clock up to 5.7GHz. The clock of the V-Cache die wasn’t disclosed but it is likely 300 to 400MHz lower than the standard CCD.
AMD also announced the Fire Range series of chips which are for all intents and purposes Zen 5 desktop chips with a slightly lower boost clock packaged into a BGA formfactor then put into desktop replacement laptops.
These chips are silimar to the Arrow Lake HX that Intel also announced at CES 2025.
Moving from a Desktop Replacement Laptop chip to a more mainstream mobile chip, AMD also announced the Ryzen AI 7 and 5 SKUs for the Ryzen AI 300 series.
The Ryzen AI 7 350 has 4 Zen 5 cores and 4 Zen 5c cores paired with 8 CUs of RDNA 3.5 clocking up to 3GHz. The 340 is a cut down version of the 350 with 3 Zen 5 cores, 3 Zen 5c cores, and 4 CUs of RDNA 3.5 at 2.9GHz.
Now, the part of the keynote that I was most excited about was Strix Halo. Strix Halo is the big APU that many folks have wanted with 16 Zen 5 cores with the full fat 512b FPU, 40 CUs of RDNA 3.5, and 256GB/s of memory bandwidth that can support up to 128GB of LPDDR5X-8000 at a TDP between 45-120 watts.
The 16 cores can clock up to 5.1GHz with a base clock of 3.0GHz and the 40 CUs of RDNA 3.5 that go up to 2.9GHz. 256GB/s likely isn’t enough for 40 CUs of RDNA 3.5 so AMD has also added a 32MB MALL cache to Strix Halo.
What wasn’t mentioned in the keynote was RDNA4 and FSR4. Seemingly those parts of the keynote were pulled at the last minute.
We did see demos of RDNA4 and FSR4 in the AMD demo room and AMD was saying that there was going to be a separate event for both RDNA4 and FSR4 but the lack of Radeon talk was felt in room.
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> Strix Halo is the big APU ... with the full fat 512b FPU
I've been wondering about this -- where do we know this from? Did they mention it in the keynote? (Also do we know if the CPU half will have full access to all the memory bandwidth (vs. only the GPU)? I assume it would, but last time I speculated about the former question, I received counterspeculation about the latter...)