Following the first generation of V-Cache found in the Zen 3 and Zen 4 X3D SKUs, AMD is now following up with the second generation of V-Cache which is a major change for AMD in terms of packaging.
Does anyone have details about how these new dies with a layer of v-cache embedded below cores are manufactured? Previously it required a separate die with the cache to be bonded to the cores die. Is it now part of a single chip? Do all zen 5 have this layer or is it a separate design?
AMD have made a distinct shift in how they implement V-Cache. Previously they used 3 separate dies stacked on top of the original CCD - the cache die and two pieces of ‘structural silicon’ to ensure even pressure distribution under a cooler.
For the new design, AMD has created a single cache die which has an equal area to that of the CCD and filled the space originally used for structural silicon with capacitors and other power delivery. The CCD is then stacked on top of this cache die to create what is in effect a slightly taller CCD with 64MB more cache and increased power delivery stability.
I hope this clears up how they’ve changed it. The bonding process is the same - they just redesigned the structure and layout of where the additional cache sits to improve cooling and as a result clock speeds.
With regards to whether all Zen 5 dies have this - they do not. This is exclusive to V-Cache SKUs still due to limited manufacturing capacity for the bonding technique.
Does anyone have details about how these new dies with a layer of v-cache embedded below cores are manufactured? Previously it required a separate die with the cache to be bonded to the cores die. Is it now part of a single chip? Do all zen 5 have this layer or is it a separate design?
AMD have made a distinct shift in how they implement V-Cache. Previously they used 3 separate dies stacked on top of the original CCD - the cache die and two pieces of ‘structural silicon’ to ensure even pressure distribution under a cooler.
For the new design, AMD has created a single cache die which has an equal area to that of the CCD and filled the space originally used for structural silicon with capacitors and other power delivery. The CCD is then stacked on top of this cache die to create what is in effect a slightly taller CCD with 64MB more cache and increased power delivery stability.
I hope this clears up how they’ve changed it. The bonding process is the same - they just redesigned the structure and layout of where the additional cache sits to improve cooling and as a result clock speeds.
With regards to whether all Zen 5 dies have this - they do not. This is exclusive to V-Cache SKUs still due to limited manufacturing capacity for the bonding technique.
> The GMI link from the CCD to the IO die is unchanged but now it has to route from the CCD down to the SRAM die into the C4 bumps.
Is there no additional latency due to this?
I would say the increased latency from bumps are super negligible compared to having extended connections in silicon or on substrate.
And clearly it isn't
Thanks. I didn't appreciate they could have their regular IFOP serdes on the top die and connect straight through the bottom die into the interposer.
Clearly not seeing they managed to make the same 3.5 cycle l3 latency reduction that zen 5 got from zen 5