Following the first generation of V-Cache found in the Zen 3 and Zen 4 X3D SKUs, AMD is now following up with the second generation of V-Cache which is a major change for AMD in terms of packaging.
> The GMI link from the CCD to the IO die is unchanged but now it has to route from the CCD down to the SRAM die into the C4 bumps.
Is there no additional latency due to this?
Clearly not seeing they managed to make the same 3.5 cycle l3 latency reduction that zen 5 got from zen 5
> The GMI link from the CCD to the IO die is unchanged but now it has to route from the CCD down to the SRAM die into the C4 bumps.
Is there no additional latency due to this?
Clearly not seeing they managed to make the same 3.5 cycle l3 latency reduction that zen 5 got from zen 5