1) It's a great pity an in-order RISC-V machine similar to A55 was not tested -- the obvious choice being SiFive's own U74 core which in the JH7110 is probably the most common RISC-V SBC and laptop SoC of the last two years, in the VisionFive 2, the Pine64 Star64, the Milk-V Mars, the DC-Roma laptop and so on.
As they say, on many tasks a well-implemented in-order CPU can be very competitive with a small OoO.
I have both VisionFive 2 (1.5 GHz) and the C910 Lichee Pi 4A (1.85 GHz). While the C910 wins most micro-benchmarks (memcpy, primes, Dhrystone and Coremark etc) on the real-world things I use a computer for the VisionFive 2 is *always* faster. Even something simple like launching emacs. It's significantly faster on building a Linux Kernel (67m35s vs 88m4s), or compiling GNU binutils & GCC or running the CoreCLR unit test suite
2) the P550 is not limited to the 1.4 GHz its being run at here. SiFive is clearly being very conservative. Eswin say the chip runs at 1.8 GHz and so do Milk-V with their "Megrez" SBC which (with 16 GB RAM) is half the price of the HiFive Premier P550 at $199 vs $399. I have one currently 4 days into transit from Arace in China to New Zealand. Perhaps I'll have it next week. A number of other people reported on Reddit that theirs have also shipped.
The Eswin SoC is a 2nd choice fallback plan after Intel apparently shut down their "Horse Creek" project using the P550. Intel said Horse Creek would be "2+ GHz" and they demonstrated a test chip running at 2.2 GHz at Intel Innovation 2022 Developer Conference in October 2022, almost 2 1/2 years ago. That had been expected to ship in summer 2023.
Any idea how the P550 or C910 compare to the A53 or A55 area- or power-wise? Since they seem roughly comparable in performance, it would be interesting to know how they compare in such metrics.
Thanks for this follow up on RISC-V! I wonder if some of the losses vs. the in-order A55 is due to the inability of especially the P550 to deal with unaligned access. You mentioned in your preceding article that unaligned access "dependent or not, confuses P550 for hundreds of cycles." That's really bad for performance, and might well nullify the advantage of being an out-of-order design vs A55s in-order. Was the T-Head similarly affected by this?
One good thing about C910 is it's a partial open-source design: https://github.com/XUANTIE-RV/openc910, so we can know what's exactly happening in uarch.
Sort of. Part of the difficulty is some parts of the source code do not seem to match both official documentation and microbenchmarking results. Perhaps they open sourced a different iteration of the code than what made it into actual designs
I have two points here:
1) It's a great pity an in-order RISC-V machine similar to A55 was not tested -- the obvious choice being SiFive's own U74 core which in the JH7110 is probably the most common RISC-V SBC and laptop SoC of the last two years, in the VisionFive 2, the Pine64 Star64, the Milk-V Mars, the DC-Roma laptop and so on.
As they say, on many tasks a well-implemented in-order CPU can be very competitive with a small OoO.
I have both VisionFive 2 (1.5 GHz) and the C910 Lichee Pi 4A (1.85 GHz). While the C910 wins most micro-benchmarks (memcpy, primes, Dhrystone and Coremark etc) on the real-world things I use a computer for the VisionFive 2 is *always* faster. Even something simple like launching emacs. It's significantly faster on building a Linux Kernel (67m35s vs 88m4s), or compiling GNU binutils & GCC or running the CoreCLR unit test suite
2) the P550 is not limited to the 1.4 GHz its being run at here. SiFive is clearly being very conservative. Eswin say the chip runs at 1.8 GHz and so do Milk-V with their "Megrez" SBC which (with 16 GB RAM) is half the price of the HiFive Premier P550 at $199 vs $399. I have one currently 4 days into transit from Arace in China to New Zealand. Perhaps I'll have it next week. A number of other people reported on Reddit that theirs have also shipped.
The Eswin SoC is a 2nd choice fallback plan after Intel apparently shut down their "Horse Creek" project using the P550. Intel said Horse Creek would be "2+ GHz" and they demonstrated a test chip running at 2.2 GHz at Intel Innovation 2022 Developer Conference in October 2022, almost 2 1/2 years ago. That had been expected to ship in summer 2023.
https://web.archive.org/web/20221101114447/https://fuse.wikichip.org/news/7277/intel-sifive-demo-high-performance-risc-v-horse-creek-dev-platform-on-intel-4-process/
Any idea how the P550 or C910 compare to the A53 or A55 area- or power-wise? Since they seem roughly comparable in performance, it would be interesting to know how they compare in such metrics.
Thanks for this follow up on RISC-V! I wonder if some of the losses vs. the in-order A55 is due to the inability of especially the P550 to deal with unaligned access. You mentioned in your preceding article that unaligned access "dependent or not, confuses P550 for hundreds of cycles." That's really bad for performance, and might well nullify the advantage of being an out-of-order design vs A55s in-order. Was the T-Head similarly affected by this?
T-HEAD is not affected. They have pretty good handling for unaligned accesses
One good thing about C910 is it's a partial open-source design: https://github.com/XUANTIE-RV/openc910, so we can know what's exactly happening in uarch.
Sort of. Part of the difficulty is some parts of the source code do not seem to match both official documentation and microbenchmarking results. Perhaps they open sourced a different iteration of the code than what made it into actual designs