Sitemap - 2022 - Chips and Cheese
Golden Cove’s Lopsided Vector Register File
Was Rocket Lake Power Efficient?
Knight’s Landing: Atom with AVX-512
Cannon Lake: Intel’s Forgotten Generation
AMD’s Zen 4, Part 2: Memory Subsystem and Conclusion
AMD’s Zen 4 Part 1: Frontend and Execution Engine
Microbenchmarking Nvidia’s RTX 4090
Addendum: Clock Ramp on ADL, Zen 4, M1, and More
Microbenchmarking Intel’s Arc A770
Skylake: Intel’s Longest Serving Architecture
Hot Chips 34 – Biren’s BR100: A Machine Learning GPU from China
China’s Phytium D2000: Building on A72?
Nvidia’s RTX 4090 Launch: A Strong Ray-Tracing Focus
Hot Chips 34 – AMD’s Instinct MI200 Architecture
How Quickly do CPUs Change Clock Speeds?
Hot Chips 34 – Intel’s Meteor Lake Chiplets, Compared to AMD’s
Hot Chips 34 – Tesla’s Dojo Microarchitecture
Tachyum’s Revised Prodigy Architecture
A Preview of Raptor Lake’s Improved L2 Caches
AMD’s Athlon 64: Getting the Basics Right
Caching Energy Efficiency Data – Mobile and AVX-512
Alder Lake’s Caching and Power Efficiency
Intel’s Netburst: Failure is a Foundation for Success
Sunny Cove: Intel’s Lost Generation
iGPU Cache Setups Compared, Including M1
Examining Centaur CHA’s Die and Implementation Goals
Centaur CHA’s Probably Unfinished Dual Socket Implementation
Intel Renames Oregon Fab: Gordon Moore Park. Adds +270k sq ft, 18A Node now 2024
GPU Hardware Video Encoders – How Good Are They?
VIA Part 4 – A Deep Dive into Centaur’s Last CPU Core: CNS
SiFive Completes Series F Funding Round: +$175m, $2.5b Evaluation
State of Windows on Arm64: a high-level perspective
Going Armchair Quarterback on Golden Cove’s Caches
Alder Lake’s Power Efficiency – A Complicated Picture