Great piece of investigative work, thanks for posting it up.
Questions:
Hardware -> DDR5-6000 28-36-36-96 (which brand of memory stick were you using?)
I'm working on setting up some RDMA networking stuff with smart NIC and trying to workout which memory-kits should i go with. Online reviews suggest more "Expensive" kits like CU-DIM to close the gaps with X3D.
CPU related
BIOS -> Intel 200S boost enabled?
Frontend Bandwidth -> "8 renamer-slots on Lion-Cove". So simple ALU/AGU instruction (4-8bytes bytecode length) it can handle the allocation of physical registers at ~8 micro-ops per cycle pass the instruction decoders?
Arbitration queue (ARB)
"The ARB runs at the CPU tile’s uncore clock, or 3.8 GHz"
**uncore" means the base-clock of the P-Cores? Can that be over-clocked?
G.Skill F5-6000J2836G16G, actually supplied by AMD, but I'm using it in the ARL system because it loads the EXPO profile just fine and it's the fastest memory I have around. I wouldn't pay too much attention to the memory specifics.
I updated the BIOS, but didn't change anything beyond enabling EXPO. I'll check later to see if the 200S boost thing is enabled
Allocation rate is just 8 micro-ops, not related to instruction length (unless you have a lot of long instructions, have a low op cache hitrate, and bottleneck the decoders from hitting L1i bandwidth limits)
The uncore clock is the clock of the ring bus, which connects the cores to L3. Its been decoupled from core clocks since Haswell. Can be overclocked (iirc it's a multiplier off a 100 mhz base clock just like with the cores), but I'm looking at the general picture rather than overclocking.
Great piece of investigative work, thanks for posting it up.
Questions:
Hardware -> DDR5-6000 28-36-36-96 (which brand of memory stick were you using?)
I'm working on setting up some RDMA networking stuff with smart NIC and trying to workout which memory-kits should i go with. Online reviews suggest more "Expensive" kits like CU-DIM to close the gaps with X3D.
CPU related
BIOS -> Intel 200S boost enabled?
Frontend Bandwidth -> "8 renamer-slots on Lion-Cove". So simple ALU/AGU instruction (4-8bytes bytecode length) it can handle the allocation of physical registers at ~8 micro-ops per cycle pass the instruction decoders?
Arbitration queue (ARB)
"The ARB runs at the CPU tile’s uncore clock, or 3.8 GHz"
**uncore" means the base-clock of the P-Cores? Can that be over-clocked?
G.Skill F5-6000J2836G16G, actually supplied by AMD, but I'm using it in the ARL system because it loads the EXPO profile just fine and it's the fastest memory I have around. I wouldn't pay too much attention to the memory specifics.
I updated the BIOS, but didn't change anything beyond enabling EXPO. I'll check later to see if the 200S boost thing is enabled
Allocation rate is just 8 micro-ops, not related to instruction length (unless you have a lot of long instructions, have a low op cache hitrate, and bottleneck the decoders from hitting L1i bandwidth limits)
The uncore clock is the clock of the ring bus, which connects the cores to L3. Its been decoupled from core clocks since Haswell. Can be overclocked (iirc it's a multiplier off a 100 mhz base clock just like with the cores), but I'm looking at the general picture rather than overclocking.