My understanding (a shallow one in the networking space to start with), it seems like the equivalent of Nvidia's offering would be Bluefield (mixing ARM cores with GPU like RISC-V cores that can launch/distribute multi light weight threads for handling data packets).
Are the P4 code usually compiled down into RISC like ISA and targeted to run on very narrow (1-2 ALU (low-cycle operations) execution ports with small scheduler entries) on the FXP pipelines?
Mount Evans has 12 × 16-bit LPDDR4-4276 channels grouped into three 64-bit groups, for a total of ~100GB/s raw DDR bandwidth.
Mount Morgan has 16 × 16-bit LPDDR5-6400 channels grouped into four 64-bit groups, for ~200GB/s raw DDR bandwidth.
Thanks Chester! Maybe I missed it, but will Intel fab Mount Morgan themselves, and in what node(s)?
My understanding (a shallow one in the networking space to start with), it seems like the equivalent of Nvidia's offering would be Bluefield (mixing ARM cores with GPU like RISC-V cores that can launch/distribute multi light weight threads for handling data packets).
https://arxiv.org/html/2402.03041v2
Question on the P4 section and the FXP pipelines:
Are the P4 code usually compiled down into RISC like ISA and targeted to run on very narrow (1-2 ALU (low-cycle operations) execution ports with small scheduler entries) on the FXP pipelines?