Question about Clearwater Forest: Did I read correctly that Intel has at minimum early Test samples of CF with tiles fabricated in 18 Angstrom? And, any mention of yield or when they'll send engineering samples to their OEMs ( Dell, HPE, Lenovo...)? Thanks!
I thought Clearwater Forest used Darkmont cores?
Base tile uses intel 3 (improved EUV node) with SRAM using "HDC" high density cell libraries
288/4 = 72 clusters
3 columns from the presentation deck - 72/3 == 24 clusters/per column
4 Skymont core forms 1 cluster -> 24*4 == 96 cores per column
Per compute tile has 24 cores (so 6 clusters) -> where each cluster has 8MB L3 + 4 MB L2 (both shared)
8MB * 6 = 48MB L3
4MB * 6 = 24MB L2
If L3 goes to 10MB (with acceptable range & increase in latency per clock cycle), that would get it close to something like AMD V-Cache.
Question about Clearwater Forest: Did I read correctly that Intel has at minimum early Test samples of CF with tiles fabricated in 18 Angstrom? And, any mention of yield or when they'll send engineering samples to their OEMs ( Dell, HPE, Lenovo...)? Thanks!
Chester, Thanks for your coverage from Hot Chips! Looking forward to the next ones!
Since I haven't been at HC myself, this request may be "off target": I am curious if there was Q&A, and if so, what you found most interesting ?