Now, keep in mind, those slides are all comparing Clearwater Forest to the previous Sierra Forest processor, which used Crestmont E-cores. There was no Intel server processor that used Skymont. Someone smarter than me will have to go through those slides, and see if all the architecture differences and perf improvements going from Crestmont to Darkmont are are really the same as going from Crestmont to Skymont - or if Darkmont does deliver further IPC improvements to Intel's E-core over Skymont.
Darkmont is probably the correct name, but Darkmont is just Skymont ported from the TSMC process to the Intel 18A process, perhaps with some corrected bugs.
i thought so too, but chester may have a point here because the only thing different that i see over Skymont is the 17cycle L2 latency down from 19ns and a hugely larger amount of L3 per Core. It is 4mb per Core or 16mb per Cluster, i think Chester mixed up his numbers so he wrote 8MB slices and 576mb total (Intels number is 1152mb of llc).
to be fair, " twice as much as the 144 cores on Sierra Forest" is only true because Sierra forrests top model 6900E never launched. But it was announced several times with 288C and it would have been needed to counter AMD Bergamo yet alone recent Turin dense.
According to Phoronix a 2P XEON 6766E is close in general Linux performance to a single socket Epyc 9754. Thats not great. CWF is desperately needed by intel DCG, not only to close the gap in performance but more to actually be available. Lets hope the chiplet approach makes them achieve the scale they need to actually release a 288C model this time around.
Edit: it should be 8MB per cluster or 192MB per intel3 base die, since the 1152 was a 2P figure.
*original comment* shouldn't it be 16MB per cluster of L3 Cache or 96MB underneath each compute tile and 384mb per base tile? Intel is quoting 1152mb of LLC which should not include the L2 cache as that is on a different die.
Question about Clearwater Forest: Did I read correctly that Intel has at minimum early Test samples of CF with tiles fabricated in 18 Angstrom? And, any mention of yield or when they'll send engineering samples to their OEMs ( Dell, HPE, Lenovo...)? Thanks!
I thought Clearwater Forest used Darkmont cores?
Intel's Clearwater Forest does indeed use Darkmont E-cores, not Skymont. If you go here (https://wccftech.com/intel-clearwater-forest-e-core-xeon-cpu-12-cpu-chiplets-18a-node-288-darkmont-cores-17-ipc-increase-2x-l2-cache-bandwidth-ddr5-8000-support/) and scroll down just a bit, you can see all of Intel's slides detailing the actual CPU architecture and IPC improvements from the previous one.
Now, keep in mind, those slides are all comparing Clearwater Forest to the previous Sierra Forest processor, which used Crestmont E-cores. There was no Intel server processor that used Skymont. Someone smarter than me will have to go through those slides, and see if all the architecture differences and perf improvements going from Crestmont to Darkmont are are really the same as going from Crestmont to Skymont - or if Darkmont does deliver further IPC improvements to Intel's E-core over Skymont.
The Next Platform is reporting that it’s Darkmont. https://www.nextplatform.com/2025/08/26/intels-clearwater-forest-xeon-7-e-core-cpu-will-be-a-beast/
Darkmont is probably the correct name, but Darkmont is just Skymont ported from the TSMC process to the Intel 18A process, perhaps with some corrected bugs.
Oh maybe. I saw them present the 9-wide decode, wide execute stage, 416 entry reorder buffer, and immediately went "Skymont".
It would be interesting if Clearwater Forest's cores got tweaks over Skymont, a bit like Crestmont over Gracemont. Too bad they didn't say
i thought so too, but chester may have a point here because the only thing different that i see over Skymont is the 17cycle L2 latency down from 19ns and a hugely larger amount of L3 per Core. It is 4mb per Core or 16mb per Cluster, i think Chester mixed up his numbers so he wrote 8MB slices and 576mb total (Intels number is 1152mb of llc).
as always the Devil is in the details
no hes right 8x72 (number of clusters) = 576mb. The 1gb of cache is for the dual socket one
ahh, sneaky intel!
to be fair, " twice as much as the 144 cores on Sierra Forest" is only true because Sierra forrests top model 6900E never launched. But it was announced several times with 288C and it would have been needed to counter AMD Bergamo yet alone recent Turin dense.
According to Phoronix a 2P XEON 6766E is close in general Linux performance to a single socket Epyc 9754. Thats not great. CWF is desperately needed by intel DCG, not only to close the gap in performance but more to actually be available. Lets hope the chiplet approach makes them achieve the scale they need to actually release a 288C model this time around.
Chester and all: Two questions regarding the data rate to L3 shown in Intel's slides (35 GB/s):
1. Is that for all four cores of the 4E cluster, and can a single core use it entirely if it's the only one needing to access L3?
2. How does that data rate compare to, let's say, Zen 5c cores accessing L3 in 5c-only EPYCs?
Base tile uses intel 3 (improved EUV node) with SRAM using "HDC" high density cell libraries
288/4 = 72 clusters
3 columns from the presentation deck - 72/3 == 24 clusters/per column
4 Skymont core forms 1 cluster -> 24*4 == 96 cores per column
Per compute tile has 24 cores (so 6 clusters) -> where each cluster has 8MB L3 + 4 MB L2 (both shared)
8MB * 6 = 48MB L3
4MB * 6 = 24MB L2
If L3 goes to 10MB (with acceptable range & increase in latency per clock cycle), that would get it close to something like AMD V-Cache.
Edit: it should be 8MB per cluster or 192MB per intel3 base die, since the 1152 was a 2P figure.
*original comment* shouldn't it be 16MB per cluster of L3 Cache or 96MB underneath each compute tile and 384mb per base tile? Intel is quoting 1152mb of LLC which should not include the L2 cache as that is on a different die.
Question about Clearwater Forest: Did I read correctly that Intel has at minimum early Test samples of CF with tiles fabricated in 18 Angstrom? And, any mention of yield or when they'll send engineering samples to their OEMs ( Dell, HPE, Lenovo...)? Thanks!
Chester, Thanks for your coverage from Hot Chips! Looking forward to the next ones!
Since I haven't been at HC myself, this request may be "off target": I am curious if there was Q&A, and if so, what you found most interesting ?