I believe the CCDs have 48 or 24 corse as amd seems to have associated the cache per CCXs of 12 with 32 cores the CCX configs would be very odd but maybe 4 CCXs of 8 would function ?
They don't seem to be able to connect coherently and with low enough latency 16 cores yet , I mean 12 cores on one CCX is crazy impressive , can't wait to read your article on how they achieved it when Zen 6 comes out !
As the loss of single core performance is not as important for the tasks it's designed for
(Unless I'm making a fool of myself and it's official info and I'm misreading) !
Zen 6c could be minuscule if built on 2nm with the same design changes that compromise frequency for die size , because if MLID is to be believed Zen 6 standard is focused on high frequencies therefore a lot of the die size and transistor budget will go towards achieving that so I'd expect zen 6c to slim down a lot if it let's go of that , also I find odd that they haven't cut the cache in half like on previous dense dies
Hey cheese , thx as always for the informative article , although I have a question , I've read up this previous article of yours to get some reminders about the MII350
And you seem to mention there it having 4 base dies yet you mention in the current article it having 2 , am I misunderstanding something or is there an error in one of the articles ?
Thx for reading and wish you all the best , and if you have the time , a clarification would be lovely as I can't find any public info on the die config either
The 256 core Venice processor must be using low clock frequency Zen6c dense cores even if AMD calls them "Zen6" cores. The Venice processor with real Zen6 (high clock frequency) cores will probably contain about 192 cores to have an achievable improvement in performance/Watt from Zen5. A 192 core Venice processor could be organized as 8 chiplets with 2 CCX per chiplet and 12 cores per CCX. Desktop processors will probably have a single CCX with 12 Zen6 (high clock frequency) cores.
The 96 core version of Genoa-X has 12MB of L3 per core. Some media outlets have reported that Venice-X will have the option for a stack of two 3D V-Cache die under each CPU chiplet. Two 3D V-Cache die would provide 4 + 8 + 8 = 20MB of L3 per core. A 192 core Venice-X Zen6 processor could have:
192 x 12MB = 2304MB = 2.25GB of total L3 (one 3D V-Cache die per CPU chiplet) or
192 x 20MB = 3840MB = 3.75GB of total L3 (two 3D V-Cache die per CPU chiplet).
For Venice-X, each high clock frequency Zen6 CCX with 12 cores per CCX would share 12 x 12MB = 144MB or 12 x 20MB = 240MB of L3 cache. For comparison, the largest Granite Rapids processor in SNC3 mode has 43 cores sharing 168MB of L3 slices, with the whole processor containing about 3x that.
"As for the compute dies, while the packaging precludes any visual demarcation of the different compute dies, it is likely that there are 8 compute dies with 4 compute dies on each base die. So while we can’t figure out the exact die size of the compute dies, the maximum size is approximately 180mm2."
So on MI400, the two large rectangular dies in the center are not the GCDs with the surrounding dies being the MCDs? Are you saying the GCDs are underneath these?
Lisa showed a rendered XCD wafer in the background video. I recreated that chip layout in die yield calculator, and my best guess is ~13.2mm*10mm with 0.1mm scribe line.
I believe the CCDs have 48 or 24 corse as amd seems to have associated the cache per CCXs of 12 with 32 cores the CCX configs would be very odd but maybe 4 CCXs of 8 would function ?
They don't seem to be able to connect coherently and with low enough latency 16 cores yet , I mean 12 cores on one CCX is crazy impressive , can't wait to read your article on how they achieved it when Zen 6 comes out !
As the loss of single core performance is not as important for the tasks it's designed for
(Unless I'm making a fool of myself and it's official info and I'm misreading) !
Zen 6c could be minuscule if built on 2nm with the same design changes that compromise frequency for die size , because if MLID is to be believed Zen 6 standard is focused on high frequencies therefore a lot of the die size and transistor budget will go towards achieving that so I'd expect zen 6c to slim down a lot if it let's go of that , also I find odd that they haven't cut the cache in half like on previous dense dies
Hey cheese , thx as always for the informative article , although I have a question , I've read up this previous article of yours to get some reminders about the MII350
https://chipsandcheese.com/p/amds-cdna-4-architecture-announcement
And you seem to mention there it having 4 base dies yet you mention in the current article it having 2 , am I misunderstanding something or is there an error in one of the articles ?
Thx for reading and wish you all the best , and if you have the time , a clarification would be lovely as I can't find any public info on the die config either
The 256 core Venice processor must be using low clock frequency Zen6c dense cores even if AMD calls them "Zen6" cores. The Venice processor with real Zen6 (high clock frequency) cores will probably contain about 192 cores to have an achievable improvement in performance/Watt from Zen5. A 192 core Venice processor could be organized as 8 chiplets with 2 CCX per chiplet and 12 cores per CCX. Desktop processors will probably have a single CCX with 12 Zen6 (high clock frequency) cores.
The 96 core version of Genoa-X has 12MB of L3 per core. Some media outlets have reported that Venice-X will have the option for a stack of two 3D V-Cache die under each CPU chiplet. Two 3D V-Cache die would provide 4 + 8 + 8 = 20MB of L3 per core. A 192 core Venice-X Zen6 processor could have:
192 x 12MB = 2304MB = 2.25GB of total L3 (one 3D V-Cache die per CPU chiplet) or
192 x 20MB = 3840MB = 3.75GB of total L3 (two 3D V-Cache die per CPU chiplet).
For Venice-X, each high clock frequency Zen6 CCX with 12 cores per CCX would share 12 x 12MB = 144MB or 12 x 20MB = 240MB of L3 cache. For comparison, the largest Granite Rapids processor in SNC3 mode has 43 cores sharing 168MB of L3 slices, with the whole processor containing about 3x that.
"As for the compute dies, while the packaging precludes any visual demarcation of the different compute dies, it is likely that there are 8 compute dies with 4 compute dies on each base die. So while we can’t figure out the exact die size of the compute dies, the maximum size is approximately 180mm2."
So on MI400, the two large rectangular dies in the center are not the GCDs with the surrounding dies being the MCDs? Are you saying the GCDs are underneath these?
Lisa showed a rendered XCD wafer in the background video. I recreated that chip layout in die yield calculator, and my best guess is ~13.2mm*10mm with 0.1mm scribe line.