6 Comments

Very interesting, I had completely forgotten about these chips.

Just one question, is there possibly a typo in the table with the SRAM physical sizes for the density-optimised Power8 SRAM? At 6T density-optimised it's more than 7 times as large than the 8T not-density-optimised SRAM on the same chip? That sounds very weird.

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Oops, yeah it should be 0.144 um2. I fixed it at https://old.chipsandcheese.com/2024/11/01/broadwells-edram-vcache-before-vcache-was-cool/

Bit harder to fix on Substack because they don't have table support

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Not a big deal - people can see the comment here in any case.

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I have fixed the image here on Substack.

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Thanks for this article! After looking at the tiles that make up Arrow Lake, I don't think I was the only one who wondered if the larger of the two filler tiles couldn't be replaced with a much more modern version of Crystal Well. As you wrote, IBM has shown that eDRAM cache can be implemented with both low latencies and high throughput. And, Arrow Lake's larger of the two current filler tile is conveniently located right next to the compute tile. Intel needs to get creative (again) and come back with a real alternative to AMD's new 3D cache design for the 9800 Ryzen. Plus, would be a good dress-rehearsal for the next Xeons.

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"high capacity caching is a fun part of Intel’s history. It would be fun to see it return."

IIRC MLID or someone else mentioned that they tried it for Meteor/Arrow lake, but the Adamantine base tile was cancelled in development due to #problems

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