Talking with Synopsys about the Physics of Chip Design at DAC 2026
Hello you fine Internet folks,
I did an audio interview with Ravi Subramanian from Synopsys where we talked about the physics that goes into chip design and EDA tools.
Hope y’all enjoy!
The transcript below has been edited for conciseness and readability.
George Cozma: At AMD’s Advancing AI was last week, you guys made some announcements there about 3DIC, and I would just like to learn a little bit more about that and hear a bit more about how you guys are thinking about thermals, but not just thermals, things like current such how to carry current from package to the compute dies?
Ravi Subramanian: So maybe a good starting point is the two main trends going on in computing from a pure silicon perspective, chips are getting bigger and bigger to the point where we have some reticle-limited chips. So we see that companies are using 2.5D and 3D types of integration techniques to have multi-die solutions to handle the ever-increasing compute complexity.
Thermals have always been a problem in chip design, so it’s not new. The first wave of big thermal innovation really had to do with the early eras of CPUs. As CPUs were getting faster and faster, how did they need to allow the device to operate in a package that’s sitting inside a laptop or sitting inside a desktop. Then came the mobile communications world brought some severe limits, because it was the first time the whole chip operation was determined by a battery-powered device.
George Cozma: Holds up phone.
Ravi Subramanian: Bingo. Exactly. All of a sudden, what was needed in doing low-power design, in terms of the EDA tools to do low-power design, and what was needed in terms of managing thermal effects not just from the compute die, but also from the power amplifier, which is sitting not so far away from the compute die in that chip, and then the battery, which is also creating heat. So all of a sudden, we now have a system where it’s not so simple to put a fan in a chassis and control things. The mobile industry really created the first step-function in how you need to think about thermal from a system perspective.
Then fast-forward, we go to automotive chips, and then we see regulations or rules really determining how the chip should operate because of the environment that it’s in.
George Cozma: So for automotive, is it less the actual thermals of the chip and more the environment of where the chip is being placed?
Ravi Subramanian: So the environment is a bigger factor, but if you look at a typical mobile SoC, it’s about 2 to 2.5 billion gates. A typical automotive ECU chip now is about 7 billion gates. So it is bigger, 3x bigger, and there are big power challenges. As a simple example, the way that’s really measured now is, “Oh, it translates into a much smaller range for the car,” because of how much energy is consumed by the compute die. So Mercedes, BMW, the US car makers, and others have talked about what’s the range restriction because of how much [power] is consumed by the chip.
Then we get to the data center, which is now another type of system with another set of constraints around the chip, the package, the rack, and then the whole building that everything is sitting in. So that’s the scale of how the thermal problem has changed, right? With different system complexity and the importance of not only the chip power dissipation and the way packaging is handled, but also the environment and what the environment brings in.
So now, if we look at 3D-IC and chip-in-package, and maybe more specifically about AMD…
George Cozma: If I remember correctly, AMD announced at their Advancing AI event which was last week and while there Synopsys announced the release of 3DIC which came with AMD as the co-partner for it.
Ravi Subramanian: Yes, yes. So AMD has been a leader since their presentation at ISSCC, I believe it was in 2019, when they disaggregated the die, and then they showed what the advantage is. That was the first seminal paper in this field that really set the stage for what’s the thinking behind going multi-die, and obviously evolving that to 2.5D and 3D.
Now, the minute you go multi-die, you get a number of advantages in terms of the total cost of the solution because of the fact that you’ve really thought about which logic node should which processing be in. But then what you’ve also done is you created a problem in that you have to move so much data around, and the energy consumed by moving the data.
So to get higher performance, Moore’s Law only gave you so much. You pick an advanced node, you can get the highest performance there, but then within a package now, you have multiple dies, each one having power dissipation during operation, which is very much related to the workload running on it.
So the first step is understanding, for a given architecture with a workload running on it, exactly how much power is consumed and where in the workload the power is actually consumed. So that’s one capability needed early on pre-silicon, that’s a verification type of problem.
And then the second piece is, once you actually have a structure or an architecture, what happens is, because of the package and because of the die, there can be warpage, and there are mechanical effects that used to be second and third-order effects and those effects now [are first-order effects], because the chips are getting bigger, you actually have mechanical effects creating a strain in the silicon, and that changes the electrical properties.
George Cozma: Okay. I know the whole joke is: if you want the best thermal dissipation, make it the size of a wafer; if you want the cheapest cost, make it the size of your fingernail.
Ravi Subramanian: Exactly! So what we have then is, in order to be able to analyze all the effects, sign-off used to be, “I’m going to make sure the functional performance of the chip is okay, I’m going to make sure the electrical performance is okay.” But now, you need to look at the mechanical-electrical pairing. And then similarly, you need to look at the thermal, and that is, as the chip is running, you have IR drop, you have electromigration, and you need to be able to analyze the performance of the chip with those effects incorporated.
And then finally, the last one is electromagnetic effects. Electromigration has to do with electrons; electromagnetics with Maxwell’s equations. So a good way to think about it is there’s Moore’s Law coming one way, and then there are all the notions of material stiff equations, partial differential equations for looking at materials and then Maxwell’s equations for electromagnetics, right? So, you know, even though people say, “Well, Moore’s Law was doubling every 18 months and you had to deal with that complexity,” 10 years ago, many of the effects we’re talking about were second and third-order effects, and didn’t really affect the performance.
George Cozma: And now it’s first-order.
Ravi Subramanian: Now it’s first-order, exactly. So the definition of what you do to sign off a chip before you give it to TSMC means you not only do the classical electrical sign-off, but you now have to co-sign-off on mechanical-electrical, thermal-electrical, electromigration, and electromagnetic. Because as you get to smaller and smaller wires, these actually behave as antennas as the signal speeds increase.
George Cozma: Yeah, effectively everything starts to become RF.
Ravi Subramanian: Exactly. So even within a package, if you have very high-speed connections, essentially you have radiating wires, right? And they could create interference because one wire is next to another where it could create a crosstalk effect, etc.
So that’s the scope of the nature of the problems AMD had to solve in successfully getting out some of the chips they announced at the Advancing AI event. We worked very closely together with them—R&D teams working with chip designers to understand what do they want to analyze, and how do we make that happen pre-silicon. Because as you may read, some of these chips now, they’re very complex multi-die or 3D-IC, and they have complex packaging, and sometimes they find a problem only after it comes out.
George Cozma: I mean, I think Jensen famously talked about the issues that they had with Blackwell.
Ravi Subramanian: Exactly. And so now people want to very much say, “How can I bring the view of those problems upfront? How can I look at those earlier and be more confident about handling them?”
George Cozma: So, I guess, going to that second part, the whole way of powering a chip via basically through TSVs and through all that, how has that changed the way that EDA tools work?
Ravi Subramanian: Sure. So a good way to think of that is maybe I’m going to start with chip and then system, right? On the chip side, today, if you look at a typical blade that’s going into many data centers, on the board you have the chips, but you also have a lot of power supplies, LDOs and other types of chips, that are managing how current is distributed across the chip.
For a very long time, the standard architecture has been 54V. As you try to push more and more signal across, the current in these wires starts getting higher and higher. So there’s a trend, an initiative that’s happening that I’ll talk about briefly, but right now, what that means is you have to carefully manage the currents on the board and have these LDOs managing how these currents are fed into these packages and then ultimately fed into the chips.
If you have I/O chips that are primarily SERDES or driving signals from chip package off the package, they have a driver strength that’s a certain amount. Whereas what you have in terms of a specific digital processing chip, you have power domains even within that chip where you’re powering up and powering down, and you want to carefully manage how current is fed to that chip and regulated to that chip. So you literally have a world of regulators regulating how currents are fed to chips.
Now, a big key trend that’s happened recently is a view to change the data center architecture and the rack standard to 800V. That’s going to dramatically reduce the magnitude of currents, steering towards 800V as a standard. Nvidia and others are driving towards that, and companies such as Bosch and others are supporting standardized components for that.
So the architecture of a board, you can expect, is going to start looking very different. Because now you have 800V, much lower current, and what you have with respect to trace lengths and how much energy is lost, because you have a much lower current, so the $I^2R$ combination of how much energy is being lost, it completely changes that equation in terms of how effective we can be in the management of the delivery of power to every packaged device.
George Cozma: Okay. And so on these 54V systems, was there a lot more thought having to be put into where certain like I/O wires. For example, where you have these big NVLink racks, you have these switches, and you need to connect the GPUs to the switches was there a lot more consideration in 54V systems and racks to how you would lay out those wires [compared to 800V systems]?
Ravi Subramanian: Absolutely. So the two main things there would be: first, you want to have high signal fidelity, so signal integrity, analysis of signal integrity with various routing topologies for those wires. That’s one piece, and that’s really artists at work using tools to see that.
And then the second one is the rate at which data rates are increasing. With each new generation of chip, you have to feed the beast, which means feeding the data from memory to the chip, and then from the chip into a switch to somewhere else, right? Those speeds are growing dramatically.
What those interfaces look like, and the introduction of new types of links between chip-to-chip, Nvidia introduced NVLink to be able to have heterogeneous systems connecting; there’s the UCIe standard, the UAL standard, all of these about chip-to-chip. But with UCIe, it’s not one standard, every company has their own view of “We want 8 lanes, we want 16 lanes, we want 12 lanes,” right?
George Cozma: If I had a nickel for every time I’ve heard that this morning, I would have two nickels—which isn’t a lot, but it’s odd that it’s happened twice! [Laughs]
Ravi Subramanian: [Laughs] Yeah! So that’s where understanding how you’re going to deal with much higher speeds comes in. Ultimately, you have to do signal integrity, but the architecture of how you’re going to connect, what standard are you going to use chip-to-chip, package-to-memory, package-to-package, package-to-switch, all come into play there.
George Cozma: Moving sort of more from just the EDA side to the IP side, right? We’ve been talking a lot about 200G networking or 200G SerDes. Moving forward, 400G is going to become the standard, although Nvidia has said that they have 400G. What is the difference between the industry standard 400G and what Nvidia is using, which I believe is called simultaneous bidirectional 200G? What exactly are the differences?
Ravi Subramanian: Sure. So today, if we look at 224G SerDes or 224G Ethernet, that’s a standard that’s well-established. That’s where a lot of IP is getting sold and put into systems and chips.
400G is not yet standardized. That standards committee is still going, and we’ve got many companies making contributions, trying to steer the standard one way or another. And there, you have what’s called PAM signaling, right? And there are a lot of different proposals with variations of that.
George Cozma: I believe the current proposals are for PAM6 or PAM8?
Ravi Subramanian: Exactly. So that’s going on there, and there’s a lot of jostling to get to a 400G standard, but there’s also a lot of jostling to get something out in 400G, though that has to essentially get adopted and become a de facto standard. In the meantime, what we’re seeing with 224G is 224G plus optical is going to extend the life of 224G. So that’s at least the standards landscape.
Now, with Nvidia and bidirectional 224, that’s really trying to pull forward a higher speed capability, not quite 400 as a standard, but very high performance, greater than 220. And by having bidirectional capability, you are able to have much greater throughput into and out of systems. So that’s the current standards landscape.
In terms of when will 400G be a standard? The way that’s going, it’s probably going to be at least a year and a half to two years towards that, just looking at how the history of standards has been. What we’re also seeing is hyperscalers are trying to create a pseudo-custom version of the standard. The standard is relatively mature, but there are specific changes that they want to make to really support the systems that they are building for their workloads and their data center architectures.
George Cozma: Well, thank you for sitting down with me.
Ravi Subramanian: Thank you!