Thanks, very interesting! Does this remind anyone else at least a little bit of Xeon Phi? Which (starting in its 2nd generation) consisted of a whole bunch of small Atom cores each with a large area for vector extensions (AVX-512). In die shots, it looked like the rest of the Atom cores were basically squeezed into a corner by the huge area for the vector extensions. So, a good decade later, is it now AMX instead of AVX?
1) From a fabrication perspective, with the RTL (and eventually GDS file done up) in place then the foundry start the work on the photo masks for new designs or reuse the old mask (for certain layers) required for litho?
2) For IPs, would using the RTL for Atom Cores (in silo) means that the MMU controller IPs have to be from Intel or a silicon design company can mix and match IPs.
e.g. Compute tile (atom core, Intel RTL) + SOC tile (with memory controller placed on SOC tile from ARM)
This remembers me of a product like Nvidia Bluefield
Where it uses scale down RISC-V with multi-threading data-packets acceleration.
Thanks, very interesting! Does this remind anyone else at least a little bit of Xeon Phi? Which (starting in its 2nd generation) consisted of a whole bunch of small Atom cores each with a large area for vector extensions (AVX-512). In die shots, it looked like the rest of the Atom cores were basically squeezed into a corner by the huge area for the vector extensions. So, a good decade later, is it now AMX instead of AVX?
If true, what a huge departure, as you said! Fascinating.
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Can Intel share even part of the x86 architecture externally without AMD's consent?
Tyvm cheese.
some technical question(s):
1) From a fabrication perspective, with the RTL (and eventually GDS file done up) in place then the foundry start the work on the photo masks for new designs or reuse the old mask (for certain layers) required for litho?
2) For IPs, would using the RTL for Atom Cores (in silo) means that the MMU controller IPs have to be from Intel or a silicon design company can mix and match IPs.
e.g. Compute tile (atom core, Intel RTL) + SOC tile (with memory controller placed on SOC tile from ARM)
This remembers me of a product like Nvidia Bluefield
Where it uses scale down RISC-V with multi-threading data-packets acceleration.
https://arxiv.org/html/2402.03041v2
Demystifying Datapath Accelerator Enhanced Off-path SmartNIC