> I also wonder if they have improved the latency of the memory subsystem.
Unlike in Meteor Lake and Arrow Lake, Panther Lake's memory controller is now on the same tile as the CPU cores. However, that was already true of Lunar Lake.
Also, the mere fact of running at a higher clock speed will help mitigate the latency penalty of using LPDDR memory (which is due to the address and data being multiplexed over the same pins).
Thanks George for the interview! As a request: could you and (or, depending on availability) Chester have a similar interview with Tom Petersen, who is (AFAIK) heading Intel's GPU development, including Xe3? Maybe he could (Intel's lawyers permitting😄) go into additional details that weren't part of the "official" video that Intel put out.
Thanks for the interview! It's a rare privilege to get someone like that to answer (or at least respond to) your best and most obscure questions!
However, I have a couple suggestions:
1. You spent the last minute of the time slot on a cheese discussion that virtually none of your viewers cares about and to plug your video. That could've been used for at least one more technical question. Asking for "likes" and subscribers could've been edited onto the end, after the interview had concluded.
2. You also wasted time trying to impress the interviewee and/or viewers with your opinions about branching behavior of different workloads. Please don't do this. Impress them with the thought and insight that goes into your questions. If you disagree with one of their answers, ask a couple follow-up questions to see if you can discover why they gave a different answer than you expected, but don't argue.
Thanks for the interview! I would have loved to hear his perspective on the Zen5's two-ahead branch predictor.
I also wonder if they have improved the latency of the memory subsystem. IMHO, that's one of the weaknesses of recent Intel CPUs.
> I also wonder if they have improved the latency of the memory subsystem.
Unlike in Meteor Lake and Arrow Lake, Panther Lake's memory controller is now on the same tile as the CPU cores. However, that was already true of Lunar Lake.
Also, the mere fact of running at a higher clock speed will help mitigate the latency penalty of using LPDDR memory (which is due to the address and data being multiplexed over the same pins).
Thanks George for the interview! As a request: could you and (or, depending on availability) Chester have a similar interview with Tom Petersen, who is (AFAIK) heading Intel's GPU development, including Xe3? Maybe he could (Intel's lawyers permitting😄) go into additional details that weren't part of the "official" video that Intel put out.
"Why is intel so bad now?"
Thanks for the interview! It's a rare privilege to get someone like that to answer (or at least respond to) your best and most obscure questions!
However, I have a couple suggestions:
1. You spent the last minute of the time slot on a cheese discussion that virtually none of your viewers cares about and to plug your video. That could've been used for at least one more technical question. Asking for "likes" and subscribers could've been edited onto the end, after the interview had concluded.
2. You also wasted time trying to impress the interviewee and/or viewers with your opinions about branching behavior of different workloads. Please don't do this. Impress them with the thought and insight that goes into your questions. If you disagree with one of their answers, ask a couple follow-up questions to see if you can discover why they gave a different answer than you expected, but don't argue.