Thanks Chester, yes, I agree, those are fascinating devices! In addition to having to manage on very little power indeed, I wonder if they mentioned anything about security, and how their designs are or can be protected. IoT devices in general have developed a poor reputation as easily exploitable, and with "always on" devices for monitoring, that must have occurred to the developers.
The original IBM 5150 PC started at 16KB RAM and a 160KB floppy drive—this is actually *more* storage and RAM than that (in addition to being clocked higher)!
As I am myself developing devices which are sometimes only powered by a single coin cell, the idle power consumption figures don't surprise me tooo much, but I like the combination with the multi-input MTTP harvester and the wake up radio.
I am not with you on the process side of things. As it is inherently difficult to get leakage current under control as the process shrinks further, the pretty much highest end ULP microprocessor is at 40nm for that reason, not for lack of money
Oh interesting. I don't know much about process nodes, and didn't know that the efficiency benefits seen with typical consumer devices on newer nodes don't apply to the really low power stuff. Thanks for sharing!
Efficiency in active mode, if things are clocked, DOES increase, don't get me wrong. But sensors (or pretty much all small embedded stuff) are 99% of the time in idle. In the past (think original AVR8), it was enough to lower the clock to the kHz range and consumption went down to the microWatt Range. Nowadays that leads to milliWatts. Instead heavy power gating is needed to keep things in check and still you regularly get new versions of an MCU which are more efficient in active mode but not quite as good as the predecessor in idle.
One STM example are WBx5 Series and WBA Series. The former has two cores, the later one, the former is produced 90nm, the later in 40nm. The later is a bit more efficient per clock, but the former can keep 256kB of SRAM active for the same amount of charge where the later only manages 16kB of retained data with 10% more power draw. So obviously leake of the SRAM cells is a magnitude worse.
Thanks Chester, yes, I agree, those are fascinating devices! In addition to having to manage on very little power indeed, I wonder if they mentioned anything about security, and how their designs are or can be protected. IoT devices in general have developed a poor reputation as easily exploitable, and with "always on" devices for monitoring, that must have occurred to the developers.
Yeah security could be a concern especially with longer range signals (like mobile networks). Hopefully the software side is solid.
Fascinating!
I agree! If their security could be hardened sufficiently, they might also be interesting for healthcare-related applications.
The original IBM 5150 PC started at 16KB RAM and a 160KB floppy drive—this is actually *more* storage and RAM than that (in addition to being clocked higher)!
As I am myself developing devices which are sometimes only powered by a single coin cell, the idle power consumption figures don't surprise me tooo much, but I like the combination with the multi-input MTTP harvester and the wake up radio.
I am not with you on the process side of things. As it is inherently difficult to get leakage current under control as the process shrinks further, the pretty much highest end ULP microprocessor is at 40nm for that reason, not for lack of money
https://www.st.com/en/microcontrollers-microprocessors/stm32u3-series.html
Oh interesting. I don't know much about process nodes, and didn't know that the efficiency benefits seen with typical consumer devices on newer nodes don't apply to the really low power stuff. Thanks for sharing!
Efficiency in active mode, if things are clocked, DOES increase, don't get me wrong. But sensors (or pretty much all small embedded stuff) are 99% of the time in idle. In the past (think original AVR8), it was enough to lower the clock to the kHz range and consumption went down to the microWatt Range. Nowadays that leads to milliWatts. Instead heavy power gating is needed to keep things in check and still you regularly get new versions of an MCU which are more efficient in active mode but not quite as good as the predecessor in idle.
One STM example are WBx5 Series and WBA Series. The former has two cores, the later one, the former is produced 90nm, the later in 40nm. The later is a bit more efficient per clock, but the former can keep 256kB of SRAM active for the same amount of charge where the later only manages 16kB of retained data with 10% more power draw. So obviously leake of the SRAM cells is a magnitude worse.
Fascinating!
A single solar cell would already increase the available energy dramatically. We already have battery-free remote controls.